Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date         : Wed May 28 14:33:36 2025
| Host         : DESKTOP-A5BALAG running 64-bit major release  (build 9200)
| Command      : report_timing -file timing_report_wallace.txt
| Design       : Eight_bit_Wallace
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
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Timing Report

Slack (VIOLATED) :        -5.737ns  (required time - arrival time)
  Source:                 B2
                            (input port clocked by virtclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            P13
                            (output port clocked by virtclk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             virtclk
  Path Type:              Max at Slow Process Corner
  Requirement:            10.000ns  (virtclk rise@10.000ns - virtclk rise@0.000ns)
  Data Path Delay:        11.712ns  (logic 4.410ns (37.654%)  route 7.302ns (62.346%))
  Logic Levels:           9  (IBUF=1 LUT4=1 LUT5=1 LUT6=5 OBUF=1)
  Input Delay:            2.000ns
  Output Delay:           2.000ns
  Clock Uncertainty:      0.025ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock virtclk rise edge)    0.000     0.000 r  
                         ideal clock network latency
                                                      0.000     0.000    
                         input delay                  2.000     2.000    
    W16                                               0.000     2.000 r  B2 (IN)
                         net (fo=0)                   0.000     2.000    B2
    W16                  IBUF (Prop_ibuf_I_O)         0.949     2.949 r  B2_IBUF_inst/O
                         net (fo=19, routed)          1.657     4.605    B2_IBUF
    SLICE_X1Y7           LUT6 (Prop_lut6_I1_O)        0.124     4.729 r  P4_OBUF_inst_i_4/O
                         net (fo=3, routed)           0.428     5.157    Full_Adder1_out2
    SLICE_X1Y8           LUT4 (Prop_lut4_I0_O)        0.124     5.281 r  P5_OBUF_inst_i_8/O
                         net (fo=5, routed)           0.850     6.131    Full_Adder7_out2
    SLICE_X3Y8           LUT6 (Prop_lut6_I0_O)        0.124     6.255 r  P7_OBUF_inst_i_6/O
                         net (fo=6, routed)           0.580     6.835    Full_Adder21_out2
    SLICE_X1Y10          LUT6 (Prop_lut6_I4_O)        0.124     6.959 r  P10_OBUF_inst_i_10/O
                         net (fo=1, routed)           0.943     7.902    Full_Adder34_out1
    SLICE_X0Y13          LUT6 (Prop_lut6_I1_O)        0.124     8.026 r  P10_OBUF_inst_i_4/O
                         net (fo=4, routed)           0.482     8.508    Full_Adder42_out2
    SLICE_X0Y13          LUT6 (Prop_lut6_I0_O)        0.124     8.632 r  P12_OBUF_inst_i_2/O
                         net (fo=3, routed)           0.509     9.140    Full_Adder44_out2
    SLICE_X1Y13          LUT5 (Prop_lut5_I4_O)        0.124     9.264 r  P13_OBUF_inst_i_1/O
                         net (fo=1, routed)           1.855    11.119    P13_OBUF
    R18                  OBUF (Prop_obuf_I_O)         2.593    13.712 r  P13_OBUF_inst/O
                         net (fo=0)                   0.000    13.712    P13
    R18                                                               r  P13 (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock virtclk rise edge)   10.000    10.000 r  
                         ideal clock network latency
                                                      0.000    10.000    
                         clock pessimism              0.000    10.000    
                         clock uncertainty           -0.025     9.975    
                         output delay                -2.000     7.975    
  -------------------------------------------------------------------
                         required time                          7.975    
                         arrival time                         -13.712    
  -------------------------------------------------------------------
                         slack                                 -5.737    




